This invention relates to apparatus and method for increasing the density of MRAM cells in a memory array.
The architecture for Magnetoresistive Random Access Memory (MRAM) is composed of a plurality or array of memory cells and a plurality of digit and bit line intersections. The magnetoresistive memory cell generally used is composed of a magnetic tunnel junction (MTJ), an isolation transistor, and the intersection of digit and bit lines. The isolation transistor is generally a N-channel field effect transistor (FET). An interconnect stack connects the isolation transistor to the MTJ device, to the bit line, and to the digit line used to create part of the magnetic field for programming the MRAM cell. A standard CMOS process that utilizes a planar interconnect backend is generally used for the integration of the MRAM cells. Planar backend interconnect schemes are found in architectures using tungsten stud or damascene copper interconnects. The interconnect stack of the CMOS process can be either Alxe2x80x94Cu or copper based interconnect materials. The number of interconnect layers in the CMOS process may vary, depending upon the specific memory and devices associated with the memory which are fabricated on the same chip. Because the memory includes hundreds of thousands of cells, even small area savings in each cell can result in major advantages in density of the memory.
Accordingly it is highly desirable to provide apparatus and a method of improving the density of MRAM cells in a memory array by reducing the area of individual MRAM cells.